Managing Memory Devices in a Storage Network

ABSTRACT

A method for managing memory in a storage network begins by monitoring a service life indicator for a plurality of solid-state memory devices in the storage network and determining whether a memory device of the plurality of solid-state memory devices is approaching an end-of-life event, where end-of-life event is based on a predetermined service life. When the memory device is approaching an end-of-life event the method continues by determining whether to migrate one or more encoded data slices from the memory device to an alternative memory device and based on a decision to migrate the one or more encoded data slices, selecting a migration scheme from a plurality of migration schemes for migrating the one or more encoded data slices. Finally, the method continues by facilitating migrating the one or more encoded data slices according to the selected migration scheme.

CROSS REFERENCE TO RELATED PATENTS

The present U.S. Utility patent application claims priority pursuant to35 U.S.C. § 120 as a continuation of U.S. Utility application Ser. No.17/356,838, entitled “Parity In a Vast Storage System Using AlternateMemory”, filed Jun. 24, 2021, which is a continuation of U.S. Utilityapplication Ser. No. 16/885,602, entitled “Predicting Usable Memory,”filed May 28, 2020, issued as U.S. Pat. No. 11,073,993 on Jul. 27, 2021,which is a continuation of U.S. Utility application Ser. No. 16/174,504,entitled “Migrating An Encoded Data Slice Based On An End-Of-Life MemoryLevel Of A Memory Device,” filed Oct. 30, 2018, issued as U.S. Pat. No.10,678,450 on Jun. 9, 2020, which is a continuation of U.S. Utilityapplication Ser. No. 13/204,061, entitled “Migrating An Encoded DataSlice Based On An End-Of-Life Memory Level Of A Memory Device,” filedAug. 5, 2011, issued as U.S. Pat. No. 10,157,002 issued on Dec. 18,2018, which claims priority pursuant to 35 U.S.C. § 119(e) to U.S.Provisional Application No. 61/377,428, entitled “Repurposing Memory InA Dispersed Storage Network,” filed Aug. 26, 2010, all of which arehereby incorporated herein by reference in their entirety and made partof the present U.S. Utility patent application for all purposes.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not Applicable

INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC

Not Applicable

BACKGROUND OF THE INVENTION Technical Field of the Invention

This invention relates generally to computing systems and moreparticularly to data storage solutions within such computing systems.

Description of Related Art

Computers are known to communicate, process, and store data. Suchcomputers range from wireless smart phones to data centers that supportmillions of web searches, stock trades, or on-line purchases every day.In general, a computing system generates data and/or manipulates datafrom one form into another. For instance, an image sensor of thecomputing system generates raw picture data and, using an imagecompression program (e.g., JPEG, MPEG, etc.), the computing systemmanipulates the raw picture data into a standardized compressed image.

With continued advances in processing speed and communication speed,computers are capable of processing real time multimedia data forapplications ranging from simple voice communications to streaming highdefinition video. As such, general-purpose information appliances arereplacing purpose-built communications devices (e.g., a telephone). Forexample, smart phones can support telephony communications, but they arealso capable of text messaging and accessing the internet to performfunctions including email, web browsing, remote applications access, andmedia communications (e.g., telephony voice, image transfer, musicfiles, video files, real time video streaming. etc.).

Each type of computer is constructed and operates in accordance with oneor more communication, processing, and storage standards. As a result ofstandardization and with advances in technology, more and moreinformation content is being converted into digital formats. Forexample, more digital cameras are now being sold than film cameras, thusproducing more digital pictures. As another example, web-basedprogramming is becoming an alternative to over the air televisionbroadcasts and/or cable broadcasts. As further examples, papers, books,video entertainment, home video, etc. are now being stored digitally,which increases the demand on the storage function of computers.

A typical computer storage system includes one or more memory devicesaligned with the needs of the various operational aspects of thecomputer's processing and communication functions. Generally, theimmediacy of access dictates what type of memory device is used. Forexample, random access memory (RAM) memory can be accessed in any randomorder with a constant response time, thus it is typically used for cachememory and main memory. By contrast, memory device technologies thatrequire physical movement such as magnetic disks, tapes, and opticaldiscs, have a variable response time as the physical movement can takelonger than the data transfer, thus they are typically used forsecondary memory (e.g., hard drive, backup memory, etc.).

A computer's storage system will be compliant with one or more computerstorage standards that include, but are not limited to, network filesystem (NFS), flash file system (FFS), disk file system (DFS), smallcomputer system interface (SCSI), internet small computer systeminterface (iSCSI), file transfer protocol (FTP), and web-baseddistributed authoring and versioning (WebDAV). These standards specifythe data storage format (e.g., files, data objects, data blocks,directories, etc.) and interfacing between the computer's processingfunction and its storage system, which is a primary function of thecomputer's memory controller.

Despite the standardization of the computer and its storage system,memory devices fail; especially commercial grade memory devices thatutilize technologies incorporating physical movement (e.g., a discdrive). For example, it is fairly common for a disc drive to routinelysuffer from bit level corruption and to completely fail after threeyears of use. One solution is to a higher-grade disc drive, which addssignificant cost to a computer.

Another solution is to utilize multiple levels of redundant disc drivesto replicate the data into two or more copies. One such redundant driveapproach is called redundant array of independent discs (RAID). In aRAID device, a RAID controller adds parity data to the original databefore storing it across the array. The parity data is calculated fromthe original data such that the failure of a disc will not result in theloss of the original data. For example, RAID 5 uses three discs toprotect data from the failure of a single disc. The parity data, andassociated redundancy overhead data, reduces the storage capacity ofthree independent discs by one third (e.g., n−1=capacity). RAID 6 canrecover from a loss of two discs and requires a minimum of four discswith a storage capacity of n−2.

While RAID addresses the memory device failure issue, it is not withoutits own failures issues that affect its effectiveness, efficiency andsecurity. For instance, as more discs are added to the array, theprobability of a disc failure increases, which increases the demand formaintenance. For example, when a disc fails, it needs to be manuallyreplaced before another disc fails and the data stored in the RAIDdevice is lost. To reduce the risk of data loss, data on a RAID deviceis typically copied on to one or more other RAID devices. While thisaddresses the loss of data issue, it raises a security issue sincemultiple copies of data are available, which increases the chances ofunauthorized access. Further, as the amount of data being stored grows,the overhead of RAID devices becomes a non-trivial efficiency issue.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

FIG. 1 is a schematic block diagram of an embodiment of a computingsystem in accordance with the invention;

FIG. 2 is a schematic block diagram of an embodiment of a computing corein accordance with the invention;

FIG. 3 is a schematic block diagram of an embodiment of a distributedstorage processing unit in accordance with the invention;

FIG. 4 is a schematic block diagram of an embodiment of a grid module inaccordance with the invention;

FIG. 5 is a diagram of an example embodiment of error coded data slicecreation in accordance with the invention;

FIG. 6A is a schematic block diagram of an embodiment of a legacycomputing system in accordance with the invention;

FIG. 6B is a graph illustrating an example of a memory status inaccordance with the invention;

FIG. 7A is a schematic block diagram of an embodiment of a hybridcomputing system in accordance with the invention;

FIG. 7B is a schematic block diagram of another embodiment of a hybridcomputing system in accordance with the invention;

FIG. 8 is a flowchart illustrating an example of repurposing a legacymemory into a dispersed storage network in accordance with theinvention;

FIG. 9A is a schematic block diagram of an embodiment of a dispersedstorage (DS) unit in accordance with the invention;

FIG. 9B is a table illustrating an example of a memory assignment tablein accordance with the invention;

FIG. 10A is a flowchart illustrating an example of adding a memory inaccordance with the invention;

FIG. 10B is a flowchart illustrating an example of allocating memory inaccordance with the invention;

FIG. 11A is a flowchart illustrating an example of storing an encodeddata slice in accordance with the invention;

FIG. 11B is a flowchart illustrating an example of retrieving an encodeddata slice in accordance with the invention;

FIG. 12 is a flowchart illustrating another example of allocating memoryin accordance with the invention;

FIG. 13A is a flowchart illustrating an example of migrating a pluralityof encoded data slices in accordance with the invention;

FIG. 13B is a flowchart illustrating an example of migrating an encodeddata slice in accordance with the invention;

FIG. 14 is a flowchart illustrating another example of allocating memoryin accordance with the invention;

FIG. 15 is a flowchart illustrating another example of allocating memoryin accordance with the invention;

FIG. 16 is a flowchart illustrating another example of allocating memoryin accordance with the invention;

FIG. 17 is a flowchart illustrating an example of migrating a memory inaccordance with the invention;

FIG. 18 is a flowchart illustrating an example of securely storing datain accordance with the invention;

FIG. 19 is a flowchart illustrating an example of storing data inaccordance with the invention;

FIG. 20 is a flowchart illustrating an example of converting legacy datato dispersed data in accordance with the invention;

FIG. 21A is a flowchart illustrating another example of convertinglegacy data to dispersed data in accordance with the invention;

FIG. 21B is a flowchart illustrating another example of convertinglegacy data to dispersed data in accordance with the invention;

FIG. 22 is a flowchart illustrating an example of decommissioning amemory in accordance with the invention;

FIG. 23A is a flowchart illustrating an example of securing legacy datain accordance with the invention;

FIG. 23B is a flowchart illustrating an example of disperse storingsecure legacy data in accordance with the invention; and

FIG. 24 is a flowchart illustrating another example of decommissioning amemory in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram of a computing system 10 thatincludes one or more of a first type of user devices 12, one or more ofa second type of user devices 14, at least one distributed storage (DS)processing unit 16, at least one DS managing unit 18, at least onestorage integrity processing unit 20, and a distributed storage network(DSN) memory 22 coupled via a network 24. The network 24 may include oneor more wireless and/or wire lined communication systems; one or moreprivate intranet systems and/or public internet systems; and/or one ormore local area networks (LAN) and/or wide area networks (WAN).

The DSN memory 22 includes a plurality of distributed storage (DS) units36 for storing data of the system. Each of the DS units 36 includes aprocessing module and memory and may be located at a geographicallydifferent site than the other DS units (e.g., one in Chicago, one inMilwaukee, etc.). The processing module may be a single processingdevice or a plurality of processing devices. Such a processing devicemay be a microprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module may have an associatedmemory and/or memory element, which may be a single memory device, aplurality of memory devices, and/or embedded circuitry of the processingmodule. Such a memory device may be a read-only memory, random accessmemory, volatile memory, non-volatile memory, static memory, dynamicmemory, flash memory, cache memory, and/or any device that storesdigital information. Note that if the processing module includes morethan one processing device, the processing devices may be centrallylocated (e.g., directly coupled together via a wired and/or wireless busstructure) or may be distributedly located (e.g., cloud computing viaindirect coupling via a local area network and/or a wide area network).Further note that when the processing module implements one or more ofits functions via a state machine, analog circuitry, digital circuitry,and/or logic circuitry, the memory and/or memory element storing thecorresponding operational instructions may be embedded within, orexternal to, the circuitry comprising the state machine, analogcircuitry, digital circuitry, and/or logic circuitry. Still further notethat, the memory element stores, and the processing module executes,hard coded and/or operational instructions corresponding to at leastsome of the steps and/or functions illustrated in FIGS. 1-24 .

Each of the user devices 12-14, the DS processing unit 16, the DSmanaging unit 18, and the storage integrity processing unit 20 may be aportable computing device (e.g., a social networking device, a gamingdevice, a cell phone, a smart phone, a personal digital assistant, adigital music player, a digital video player, a laptop computer, ahandheld computer, a video game controller, and/or any other portabledevice that includes a computing core) and/or a fixed computing device(e.g., a personal computer, a computer server, a cable set-top box, asatellite receiver, a television set, a printer, a fax machine, homeentertainment equipment, a video game console, and/or any type of homeor office computing equipment). Such a portable or fixed computingdevice includes a computing core 26 and one or more interfaces 30, 32,and/or 33. An embodiment of the computing core 26 will be described withreference to FIG. 2 .

With respect to the interfaces, each of the interfaces 30, 32, and 33includes software and/or hardware to support one or more communicationlinks via the network 24 and/or directly. For example, interfaces 30support a communication link (wired, wireless, direct, via a LAN, viathe network 24, etc.) between the first type of user device 14 and theDS processing unit 16. As another example, DSN interface 32 supports aplurality of communication links via the network 24 between the DSNmemory 22 and the DS processing unit 16, the first type of user device12, and/or the storage integrity processing unit 20. As yet anotherexample, interface 33 supports a communication link between the DSmanaging unit 18 and any one of the other devices and/or units 12, 14,16, 20, and/or 22 via the network 24.

In general and with respect to data storage, the system 10 supportsthree primary functions: distributed network data storage management,distributed data storage and retrieval, and data storage integrityverification. In accordance with these three primary functions, data canbe distributedly stored in a plurality of physically different locationsand subsequently retrieved in a reliable and secure manner regardless offailures of individual storage devices, failures of network equipment,the duration of storage, the amount of data being stored, attempts athacking the data, etc.

The DS managing unit 18 performs distributed network data storagemanagement functions, which include establishing distributed datastorage parameters, performing network operations, performing networkadministration, and/or performing network maintenance. The DS managingunit 18 establishes the distributed data storage parameters (e.g.,allocation of virtual DSN memory space, distributed storage parameters,security parameters, billing information, user profile information,etc.) for one or more of the user devices 12-14 (e.g., established forindividual devices, established for a user group of devices, establishedfor public access by the user devices, etc.). For example, the DSmanaging unit 18 coordinates the creation of a vault (e.g., a virtualmemory block) within the DSN memory 22 for a user device (for a group ofdevices, or for public access). The DS managing unit 18 also determinesthe distributed data storage parameters for the vault. In particular,the DS managing unit 18 determines a number of slices (e.g., the numberthat a data segment of a data file and/or data block is partitioned intofor distributed storage) and a read threshold value (e.g., the minimumnumber of slices required to reconstruct the data segment).

As another example, the DS managing module 18 creates and stores,locally or within the DSN memory 22, user profile information. The userprofile information includes one or more of authentication information,permissions, and/or the security parameters. The security parameters mayinclude one or more of encryption/decryption scheme, one or moreencryption keys, key generation scheme, and data encoding/decodingscheme.

As yet another example, the DS managing unit 18 creates billinginformation for a particular user, user group, vault access, publicvault access, etc. For instance, the DS managing unit 18 tracks thenumber of times user accesses a private vault and/or public vaults,which can be used to generate a per-access bill. In another instance,the DS managing unit 18 tracks the amount of data stored and/orretrieved by a user device and/or a user group, which can be used togenerate a per-data-amount bill.

The DS managing unit 18 also performs network operations, networkadministration, and/or network maintenance. As at least part ofperforming the network operations and/or administration, the DS managingunit 18 monitors performance of the devices and/or units of the system10 for potential failures, determines the devices and/or unit'sactivation status, determines the devices' and/or units' loading, andany other system level operation that affects the performance level ofthe system 10. For example, the DS managing unit 18 receives andaggregates network management alarms, alerts, errors, statusinformation, performance information, and messages from the devices12-14 and/or the units 16, 20, 22. For example, the DS managing unit 18receives a simple network management protocol (SNMP) message regardingthe status of the DS processing unit 16.

The DS managing unit 18 performs the network maintenance by identifyingequipment within the system 10 that needs replacing, upgrading,repairing, and/or expanding. For example, the DS managing unit 18determines that the DSN memory 22 needs more DS units 36 or that one ormore of the DS units 36 needs updating.

The second primary function (i.e., distributed data storage andretrieval) begins and ends with a user device 12-14. For instance, if asecond type of user device 14 has a data file 38 and/or data block 40 tostore in the DSN memory 22, it send the data file 38 and/or data block40 to the DS processing unit 16 via its interface 30. As will bedescribed in greater detail with reference to FIG. 2 , the interface 30functions to mimic a conventional operating system (OS) file systeminterface (e.g., network file system (NFS), flash file system (FFS),disk file system (DFS), file transfer protocol (FTP), web-baseddistributed authoring and versioning (WebDAV), etc.) and/or a blockmemory interface (e.g., small computer system interface (SCSI), internetsmall computer system interface (iSCSI), etc.). In addition, theinterface 30 may attach a user identification code (ID) to the data file38 and/or data block 40.

The DS processing unit 16 receives the data file 38 and/or data block 40via its interface 30 and performs a distributed storage (DS) process 34thereon (e.g., an error coding dispersal storage function). The DSprocessing 34 begins by partitioning the data file 38 and/or data block40 into one or more data segments, which is represented as Y datasegments. For example, the DS processing 34 may partition the data file38 and/or data block 40 into a fixed byte size segment (e.g., 2¹ to2^(n) bytes, where n=>2) or a variable byte size (e.g., change byte sizefrom segment to segment, or from groups of segments to groups ofsegments, etc.).

For each of the Y data segments, the DS processing 34 error encodes(e.g., forward error correction (FEC), information dispersal algorithm,or error correction coding) and slices (or slices then error encodes)the data segment into a plurality of error coded (EC) data slices 42-48,which is represented as X slices per data segment. The number of slices(X) per segment, which corresponds to a number of pillars n, is set inaccordance with the distributed data storage parameters and the errorcoding scheme. For example, if a Reed-Solomon (or other FEC scheme) isused in an n/k system, then a data segment is divided into n slices,where k number of slices is needed to reconstruct the original data(i.e., k is the threshold). As a few specific examples, the n/k factormay be 5/3; 6/4; 8/6; 8/5; 16/10.

For each slice 42-48, the DS processing unit 16 creates a unique slicename and appends it to the corresponding slice 42-48. The slice nameincludes universal DSN memory addressing routing information (e.g.,virtual memory addresses in the DSN memory 22) and user-specificinformation (e.g., user ID, file name, data block identifier, etc.).

The DS processing unit 16 transmits the plurality of EC slices 42-48 toa plurality of DS units 36 of the DSN memory 22 via the DSN interface 32and the network 24. The DSN interface 32 formats each of the slices fortransmission via the network 24. For example, the DSN interface 32 mayutilize an internet protocol (e.g., TCP/IP, etc.) to packetize theslices 42-48 for transmission via the network 24.

The number of DS units 36 receiving the slices 42-48 is dependent on thedistributed data storage parameters established by the DS managing unit18. For example, the DS managing unit 18 may indicate that each slice isto be stored in a different DS unit 36. As another example, the DSmanaging unit 18 may indicate that like slice numbers of different datasegments are to be stored in the same DS unit 36. For example, the firstslice of each of the data segments is to be stored in a first DS unit36, the second slice of each of the data segments is to be stored in asecond DS unit 36, etc. In this manner, the data is encoded anddistributedly stored at physically diverse locations to improved datastorage integrity and security. Further examples of encoding the datasegments will be provided with reference to one or more of FIGS. 2-24 .

Each DS unit 36 that receives a slice 42-48 for storage translates thevirtual DSN memory address of the slice into a local physical addressfor storage. Accordingly, each DS unit 36 maintains a virtual tophysical memory mapping to assist in the storage and retrieval of data.

The first type of user device 12 performs a similar function to storedata in the DSN memory 22 with the exception that it includes the DSprocessing. As such, the device 12 encodes and slices the data fileand/or data block it has to store. The device then transmits the slices11 to the DSN memory via its DSN interface 32 and the network 24.

For a second type of user device 14 to retrieve a data file or datablock from memory, it issues a read command via its interface 30 to theDS processing unit 16. The DS processing unit 16 performs the DSprocessing 34 to identify the DS units 36 storing the slices of the datafile and/or data block based on the read command. The DS processing unit16 may also communicate with the DS managing unit 18 to verify that theuser device 14 is authorized to access the requested data.

Assuming that the user device is authorized to access the requesteddata, the DS processing unit 16 issues slice read commands to at least athreshold number of the DS units 36 storing the requested data (e.g., toat least 10 DS units for a 16/10 error coding scheme). Each of the DSunits 36 receiving the slice read command, verifies the command,accesses its virtual to physical memory mapping, retrieves the requestedslice, or slices, and transmits it to the DS processing unit 16.

Once the DS processing unit 16 has received a read threshold number ofslices for a data segment, it performs an error decoding function andde-slicing to reconstruct the data segment. When Y number of datasegments has been reconstructed, the DS processing unit 16 provides thedata file 38 and/or data block 40 to the user device 14. Note that thefirst type of user device 12 performs a similar process to retrieve adata file and/or data block.

The storage integrity processing unit 20 performs the third primaryfunction of data storage integrity verification. In general, the storageintegrity processing unit 20 periodically retrieves slices 45, and/orslice names, of a data file or data block of a user device to verifythat one or more slices have not been corrupted or lost (e.g., the DSunit failed). The retrieval process mimics the read process previouslydescribed.

If the storage integrity processing unit 20 determines that one or moreslices is corrupted or lost, it rebuilds the corrupted or lost slice(s)in accordance with the error coding scheme. The storage integrityprocessing unit 20 stores the rebuild slice, or slices, in theappropriate DS unit(s) 36 in a manner that mimics the write processpreviously described.

FIG. 2 is a schematic block diagram of an embodiment of a computing core26 that includes a processing module 50, a memory controller 52, mainmemory 54, a video graphics processing unit 55, an input/output (IO)controller 56, a peripheral component interconnect (PCI) interface 58,at least one 10 device interface module 62, a read only memory (ROM)basic input output system (BIOS) 64, and one or more memory interfacemodules. The memory interface module(s) includes one or more of auniversal serial bus (USB) interface module 66, a host bus adapter (HBA)interface module 68, a network interface module 70, a flash interfacemodule 72, a hard drive interface module 74, and a DSN interface module76. Note the DSN interface module 76 and/or the network interface module70 may function as the interface 30 of the user device 14 of FIG. 1 .Further note that the 10 device interface module 62 and/or the memoryinterface modules may be collectively or individually referred to as 10ports.

The processing module 50 may be a single processing device or aplurality of processing devices. Such a processing device may be amicroprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module 50 may have anassociated memory and/or memory element, which may be a single memorydevice, a plurality of memory devices, and/or embedded circuitry of theprocessing module 50. Such a memory device may be a read-only memory,random access memory, volatile memory, non-volatile memory, staticmemory, dynamic memory, flash memory, cache memory, and/or any devicethat stores digital information. Note that if the processing module 50includes more than one processing device, the processing devices may becentrally located (e.g., directly coupled together via a wired and/orwireless bus structure) or may be distributedly located (e.g., cloudcomputing via indirect coupling via a local area network and/or a widearea network). Further note that when the processing module 50implements one or more of its functions via a state machine, analogcircuitry, digital circuitry, and/or logic circuitry, the memory and/ormemory element storing the corresponding operational instructions may beembedded within, or external to, the circuitry comprising the statemachine, analog circuitry, digital circuitry, and/or logic circuitry.Still further note that, the memory element stores, and the processingmodule 50 executes, hard coded and/or operational instructionscorresponding to at least some of the steps and/or functions illustratedin FIGS. 1-24 .

FIG. 3 is a schematic block diagram of an embodiment of a dispersedstorage (DS) processing module 34 of user device 12 and/or of the DSprocessing unit 16. The DS processing module 34 includes a gatewaymodule 78, an access module 80, a grid module 82, and a storage module84. The DS processing module 34 may also include an interface 30 and theDSnet interface 32 or the interfaces 68 and/or 70 may be part of user 12or of the DS processing unit 14. The DS processing module 34 may furtherinclude a bypass/feedback path between the storage module 84 to thegateway module 78. Note that the modules 78-84 of the DS processingmodule 34 may be in a single unit or distributed across multiple units.

In an example of storing data, the gateway module 78 receives anincoming data object that includes a user ID field 86, an object namefield 88, and the data field 40 and may also receive correspondinginformation that includes a process identifier (e.g., an internalprocess/application ID), metadata, a file system directory, a blocknumber, a transaction message, a user device identity (ID), a dataobject identifier, a source name, and/or user information. The gatewaymodule 78 authenticates the user associated with the data object byverifying the user ID 86 with the managing unit 18 and/or anotherauthenticating unit.

When the user is authenticated, the gateway module 78 obtains userinformation from the management unit 18, the user device, and/or theother authenticating unit. The user information includes a vaultidentifier, operational parameters, and user attributes (e.g., userdata, billing information, etc.). A vault identifier identifies a vault,which is a virtual memory space that maps to a set of DS storage units36. For example, vault 1 (i.e., user 1's DSN memory space) includeseight DS storage units (X=8 wide) and vault 2 (i.e., user 2's DSN memoryspace) includes sixteen DS storage units (X=16 wide). The operationalparameters may include an error coding algorithm, the width n (number ofpillars X or slices per segment for this vault), a read threshold T, awrite threshold, an encryption algorithm, a slicing parameter, acompression algorithm, an integrity check method, caching settings,parallelism settings, and/or other parameters that may be used to accessthe DSN memory layer.

The gateway module 78 uses the user information to assign a source name35 to the data. For instance, the gateway module 60 determines thesource name 35 of the data object 40 based on the vault identifier andthe data object. For example, the source name may contain a fileidentifier (ID), a vault generation number, a reserved field, and avault identifier (ID). As another example, the gateway module 78 maygenerate the file ID based on a hash function of the data object 40.Note that the gateway module 78 may also perform message conversion,protocol conversion, electrical conversion, optical conversion, accesscontrol, user identification, user information retrieval, trafficmonitoring, statistics generation, configuration, management, and/orsource name determination.

The access module 80 receives the data object 40 and creates a series ofdata segments 1 through Y 90-92 in accordance with a data storageprotocol (e.g., file storage system, a block storage system, and/or anaggregated block storage system). The number of segments Y may be chosenor randomly assigned based on a selected segment size and the size ofthe data object. For example, if the number of segments is chosen to bea fixed number, then the size of the segments varies as a function ofthe size of the data object. For instance, if the data object is animage file of 4,194,304 eight bit bytes (e.g., 33,554,432 bits) and thenumber of segments Y=131,072, then each segment is 256 bits or 32 bytes.As another example, if segment sized is fixed, then the number ofsegments Y varies based on the size of data object. For instance, if thedata object is an image file of 4,194,304 bytes and the fixed size ofeach segment is 4,096 bytes, the then number of segments Y=1,024. Notethat each segment is associated with the same source name.

The grid module 82 receives the data segments and may manipulate (e.g.,compression, encryption, cyclic redundancy check (CRC), etc.) each ofthe data segments before performing an error coding function of theerror coding dispersal storage function to produce a pre-manipulateddata segment. After manipulating a data segment, if applicable, the gridmodule 82 error encodes (e.g., Reed-Solomon, Convolution encoding,Trellis encoding, etc.) the data segment or manipulated data segmentinto X error coded data slices 42-44.

The value X, or the number of pillars (e.g., X=16), is chosen as aparameter of the error coding dispersal storage function. Otherparameters of the error coding dispersal function include a readthreshold T, a write threshold W, etc. The read threshold (e.g., T=10,when X=16) corresponds to the minimum number of error-free error codeddata slices required to reconstruct the data segment. In other words,the DS processing module 34 can compensate for X-T (e.g., 16-10=6)missing error coded data slices per data segment. The write threshold Wcorresponds to a minimum number of DS storage units that acknowledgeproper storage of their respective data slices before the DS processingmodule indicates proper storage of the encoded data segment. Note thatthe write threshold is greater than or equal to the read threshold for agiven number of pillars (X).

For each data slice of a data segment, the grid module 82 generates aunique slice name 37 and attaches it thereto. The slice name 37 includesa universal routing information field and a vault specific field and maybe 48 bytes (e.g., 24 bytes for each of the universal routinginformation field and the vault specific field). As illustrated, theuniversal routing information field includes a slice index, a vault ID,a vault generation, and a reserved field. The slice index is based onthe pillar number and the vault ID and, as such, is unique for eachpillar (e.g., slices of the same pillar for the same vault for anysegment will share the same slice index). The vault specific fieldincludes a data name, which includes a file ID and a segment number(e.g., a sequential numbering of data segments 1-Y of a simple dataobject or a data block number).

Prior to outputting the error coded data slices of a data segment, thegrid module may perform post-slice manipulation on the slices. Ifenabled, the manipulation includes slice level compression, encryption,CRC, addressing, tagging, and/or other manipulation to improve theeffectiveness of the computing system.

When the error coded data slices of a data segment are ready to beoutputted, the grid module 82 determines which of the DS storage units36 will store the EC data slices based on a dispersed storage memorymapping associated with the user's vault and/or DS storage unitattributes. The DS storage unit attributes may include availability,self-selection, performance history, link speed, link latency,ownership, available DSN memory, domain, cost, a prioritization scheme,a centralized selection message from another source, a lookup table,data ownership, and/or any other factor to optimize the operation of thecomputing system. Note that the number of DS storage units 36 is equalto or greater than the number of pillars (e.g., X) so that no more thanone error coded data slice of the same data segment is stored on thesame DS storage unit 36. Further note that EC data slices of the samepillar number but of different segments (e.g., EC data slice 1 of datasegment 1 and EC data slice 1 of data segment 2) may be stored on thesame or different DS storage units 36.

The storage module 84 performs an integrity check on the outboundencoded data slices and, when successful, identifies a plurality of DSstorage units based on information provided by the grid module 82. Thestorage module 84 then outputs the encoded data slices 1 through X ofeach segment 1 through Y to the DS storage units 36. Each of the DSstorage units 36 stores its EC data slice(s) and maintains a localvirtual DSN address to physical location table to convert the virtualDSN address of the EC data slice(s) into physical storage addresses.

In an example of a read operation, the user device 12 and/or 14 sends aread request to the DS processing unit 14, which authenticates therequest. When the request is authentic, the DS processing unit 14 sendsa read message to each of the DS storage units 36 storing slices of thedata object being read. The slices are received via the DSnet interface32 and processed by the storage module 84, which performs a parity checkand provides the slices to the grid module 82 when the parity check wassuccessful. The grid module 82 decodes the slices in accordance with theerror coding dispersal storage function to reconstruct the data segment.The access module 80 reconstructs the data object from the data segmentsand the gateway module 78 formats the data object for transmission tothe user device.

FIG. 4 is a schematic block diagram of an embodiment of a grid module 82that includes a control unit 73, a pre-slice manipulator 75, an encoder77, a slicer 79, a post-slice manipulator 81, a pre-slice de-manipulator83, a decoder 85, a de-slicer 87, and/or a post-slice de-manipulator 89.Note that the control unit 73 may be partially or completely external tothe grid module 82. For example, the control unit 73 may be part of thecomputing core at a remote location, part of a user device, part of theDS managing unit 18, or distributed amongst one or more DS storageunits.

In an example of write operation, the pre-slice manipulator 75 receivesa data segment 90-92 and a write instruction from an authorized userdevice. The pre-slice manipulator 75 determines if pre-manipulation ofthe data segment 90-92 is required and, if so, what type. The pre-slicemanipulator 75 may make the determination independently or based oninstructions from the control unit 73, where the determination is basedon a computing system-wide predetermination, a table lookup, vaultparameters associated with the user identification, the type of data,security requirements, available DSN memory, performance requirements,and/or other metadata.

Once a positive determination is made, the pre-slice manipulator 75manipulates the data segment 90-92 in accordance with the type ofmanipulation. For example, the type of manipulation may be compression(e.g., Lempel-Ziv-Welch, Huffman, Golomb, fractal, wavelet, etc.),signatures (e.g., Digital Signature Algorithm (DSA), Elliptic Curve DSA,Secure Hash Algorithm, etc.), watermarking, tagging, encryption (e.g.,Data Encryption Standard, Advanced Encryption Standard, etc.), addingmetadata (e.g., time/date stamping, user information, file type, etc.),cyclic redundancy check (e.g., CRC32), and/or other data manipulationsto produce the pre-manipulated data segment.

The encoder 77 encodes the pre-manipulated data segment 92 using aforward error correction (FEC) encoder (and/or other type of erasurecoding and/or error coding) to produce an encoded data segment 94. Theencoder 77 determines which forward error correction algorithm to usebased on a predetermination associated with the user's vault, a timebased algorithm, user direction, DS managing unit direction, controlunit direction, as a function of the data type, as a function of thedata segment 92 metadata, and/or any other factor to determine algorithmtype. The forward error correction algorithm may be Golay,Multidimensional parity, Reed-Solomon, Hamming, Bose Ray ChauduriHocquenghem (BCH), Cauchy-Reed-Solomon, or any other FEC encoder. Notethat the encoder 77 may use a different encoding algorithm for each datasegment 92, the same encoding algorithm for the data segments 92 of adata object, or a combination thereof.

The encoded data segment 94 is of greater size than the data segment 92by the overhead rate of the encoding algorithm by a factor of X/T, whereX is the width or number of slices, and T is the read threshold. In thisregard, the corresponding decoding process can accommodate at most X-Tmissing EC data slices and still recreate the data segment 92. Forexample, if X=16 and T=10, then the data segment 92 will be recoverableas long as 10 or more EC data slices per segment are not corrupted.

The slicer 79 transforms the encoded data segment 94 into EC data slicesin accordance with the slicing parameter from the vault for this userand/or data segment 92. For example, if the slicing parameter is X=16,then the slicer 79 slices each encoded data segment 94 into 16 encodedslices.

The post-slice manipulator 81 performs, if enabled, post-manipulation onthe encoded slices to produce the EC data slices. If enabled, thepost-slice manipulator 81 determines the type of post-manipulation,which may be based on a computing system-wide predetermination,parameters in the vault for this user, a table lookup, the useridentification, the type of data, security requirements, available DSNmemory, performance requirements, control unit directed, and/or othermetadata. Note that the type of post-slice manipulation may includeslice level compression, signatures, encryption, CRC, addressing,watermarking, tagging, adding metadata, and/or other manipulation toimprove the effectiveness of the computing system.

In an example of a read operation, the post-slice de-manipulator 89receives at least a read threshold number of EC data slices and performsthe inverse function of the post-slice manipulator 81 to produce aplurality of encoded slices. The de-slicer 87 de-slices the encodedslices to produce an encoded data segment 94. The decoder 85 performsthe inverse function of the encoder 77 to recapture the data segment90-92. The pre-slice de-manipulator 83 performs the inverse function ofthe pre-slice manipulator 75 to recapture the data segment 90-92.

FIG. 5 is a diagram of an example of slicing an encoded data segment 94by the slicer 79. In this example, the encoded data segment 94 includesthirty-two bits, but may include more or less bits. The slicer 79disperses the bits of the encoded data segment 94 across the EC dataslices in a pattern as shown. As such, each EC data slice does notinclude consecutive bits of the data segment 94 reducing the impact ofconsecutive bit failures on data recovery. For example, if EC data slice2 (which includes bits 1, 5, 9, 13, 17, 25, and 29) is unavailable(e.g., lost, inaccessible, or corrupted), the data segment can bereconstructed from the other EC data slices (e.g., 1, 3 and 4 for a readthreshold of 3 and a width of 4).

FIG. 6A is a schematic block diagram of an embodiment of a legacycomputing system. The system includes a plurality of memories 102-106, aplurality of memory units 108-110, a memory bus 118, and a computingcore 26. The memory units 108-110 may include a plurality of memories112-116. The memories 102-106 and 112-116 may include one or more of amagnetic hard drives, a solid state memory, a tape drive, and opticalmemory, or any other type of memory technology to store and retrievedata. The memories 102-106 and 112-116 may have varying capacities. Forexample, memory 102 has a 500 gigabyte (GB) capacity, memory 104 as a 1terabyte (TB) capacity, and memory 106 as a 2 TB capacity. The memories102-106 and 110-116 may be implemented with different models ofdifferent manufacturers.

The memories 102-106 and 112-116 are operably coupled to the computingcore 26 via the memory bus 118 to facilitate transfer of data 120-124and data 126-132. For example, memory 104 communicates data 122 with thecomputing core 26. The computing core 26 may store replicated copies ofthe same data in two or more of the memories. For example, computingcore 26 stores a first copy of data in memory 106 and a second copy ofthe data in memory 114. As another example, computing core 26 stores thefirst copy of data in memory 112 and a second copy of the data in memory116 when the data is to be replicated within a single memory unit 108.

A typical memory of the memories 102-106 and 112-116 may fail from timeto time as the memory ages beyond a usable memory lifetime period.Memory costs of the computing system include memory replacement costsand memory cost over the usable memory life. The memory cost over theusable memory life includes the memory cost divided by the usable memorylifetime period. Lowering the memory cost lowers the memory costs of thecomputing system. Extending the usable memory lifetime period lowers thememory costs of the computing system. Replacing the memory impacts costof the legacy computing system based on a memory replacement cost and amemory disposal cost.

FIG. 6B is a graph illustrating an example of a memory status. The graphdepicts usable memory (e.g., capacity) over time for a memory device(e.g., a magnetic hard disk drive). Usability is divided into fourcategories including a level 1 usability, a level 2 usability, a level 3usability, and an unusable level. Note that a maximum amount of usablememory is available during the level 1 time period. A degradation ofusable memory occurs over time as the memory device ages. For example, ahard failure abruptly changes the usable memory level from a usablelevel (e.g., level 1) to the unusable level. As another example, softfailures may gradually change the usable level from level 1 to level 2to level 3 to the unusable level when the usable memory is below athreshold.

The memories 102-106 and 112-116 may be of different ages with respectto initial use such that some memories may fail sooner than othermemories. Each memory may follow the memory status curve of the graph indifferent ways. Analyzing or predicting a memory status of a memory mayprovide an improvement in memory utilization by avoiding use of a memorythat is not favorable for storing data based on an associated storagerequirement of the data. A catastrophic loss of data may occur if onlyone copy of data is stored on a memory that follows the soft failurecurve such that eventually the data is no longer retrievable. Acatastrophic loss of data may not occur when one pillar of encoded dataslices, produced using an error coding dispersal storage function, isstored on a memory that follows the soft failure curve such thateventually the pillars is no longer retrievable. In such a scenario, thedata may still be retrievable when a threshold number of encoded dataslices from other memories can be retrieved. A single memory failure maybe much less likely to cause a catastrophic loss of data when the memoryis utilized in a dispersed storage network. An improvement to theoverall usable memory life may be provided by migrating a memory from alegacy memory system to a dispersed storage network. The method ofmigrating a memory from the legacy memory system to the dispersedstorage network is discussed in greater detail with reference to FIGS.7A-24 .

FIGS. 7A-7B illustrates a memory migration scenario illustrating howdata contained in a memory of a legacy computing system may be migratedto a dispersed storage network (DSN) and how the memory may bephysically repurposed in the dispersed storage to store encoded dataslices rather than data (e.g., whole data objects). A reliability andavailability improvement of the data may be provided in such a migrationscenario since the data is stored as encoded data slices and failure ofthe memory may not impact data availability. An improvement in theuseful life of the memory may be provided in the migration scenariosince a failure of a memory in the DSN may not impact data availabilityto the degree that a failure of the memory when utilized in the legacycomputing system. The method of operation of migrating data and memoriesfrom a legacy computing system to a DSN is discussed in greater detailwith reference to FIGS. 8-24 .

FIG. 7A is a schematic block diagram of an embodiment of a hybridcomputing system. The hybrid computing system includes a legacycomputing system operably coupled to a dispersed storage network (DSN).The system includes a plurality of memories 102-106, a plurality ofmemory units 108-110, a memory bus 118, a computing core 26, a dispersedstorage (DS) processing unit 16, and a DSN memory 22. As illustrated,the DSN memory 22 includes a plurality of DS units 36. Memory unit 108includes a plurality of memories 112-116. The computing core 26interoperates with the DS processing unit 16 as described below.

The DS processing unit 16 encodes data utilizing an error codingdispersal storage function to produce encoded data slices 11. The DSprocessing unit 16 outputs the encoded data slices 11 to the DSN memory22 for storage. The DS processing unit 16 retrieves encoded data slices11 from the DSN memory and decodes the encoded data slices 11 utilizingthe error coding dispersal storage function to reproduce the data. In anexample of operation, the computing core 26 retrieves data 122 frommemory 104 when memory device 104 has an expired usable memory life withrespect to a legacy storage protocol utilized by the legacy computingsystem. The computing core 26 sends the data 122 to the DS processingunit 16. The DS processing unit 16 encodes the data 122 utilizing theerror coding dispersal storage function to produce encoded data slicesof data 122. The DS processing unit 16 sends the encoded data slices 11to the DSN memory 22 for storage in a plurality of DS units 36. Notethat the computing core 26 may retrieve the data 122 either from memory104 or from the DS processing unit 16. The computing core 26 retrievesthe data 122 from the DS processing unit 16 when the memory 104 isremoved from the legacy computing system. The method of retrieval ofdata 122 is discussed in greater detail with reference to FIG. 7B.

FIG. 7B is another schematic block diagram of another embodiment of ahybrid computing system. The hybrid computing system includes a legacycomputing system and a dispersed storage network (DSN). The systemincludes a plurality of memories 102-106, a plurality of memory units108-110, a memory bus 118, a computing core 26, a dispersed storage (DS)processing unit 16, and a DSN memory 22. The memory 104 is physicallymoved from the legacy computing system (e.g., disconnected from thememory bus 118 as shown in FIG. 7A) to the DSN when the memory 104 hasan expired usable memory life and data 122 has been extracted from thememory 104. The memory 104 is utilized as a DS unit 36 as part of theDSN memory 22 when memory 104 is moved to the DSN. For example, thememory 104 receives encoded data slices for storage from the DSprocessing unit 16. As another example, the memory 104 outputs encodeddata slices to the DS processing unit 16 in response to a retrievalrequest.

In an example of operation, the computing core 26 sends a retrievalrequest to the DS processing unit 16 for data 122. The DS processingunit 16 retrieves encoded data slices 11 from the DSN memory 22. The DSprocessing unit 16 decodes the encoded data slices 11 utilizing an errorcoding dispersal storage function to reproduce the data 122. The DSprocessing unit 16 outputs the data 122 to the computing core 26. In aninstance, at least some of the encoded data slices 11 (e.g., of data122) are stored within the memory 104. In another instance, none of theencoded data slices 11 (e.g., of data 122) are stored within the memory104.

FIG. 8 is a flowchart illustrating an example of repurposing a legacymemory into a dispersed storage network. The method begins with step 140where a processing module (e.g., of a dispersed storage (DS) unit)identifies a memory device having an expired useable memory life withrespect to a legacy storage protocol (e.g., redundant array ofindependent disks (RAID)). The identifying the memory device forreprovisioning prior to expiration of the useable memory life is basedon at least one of a network management message, a memory device usablememory life age indicator, a usable memory life age threshold, a userinput, an error message, a configuration message, a replacementschedule, an available memory message, a memory device insertiondetector output, a message, and a command. For example, the processingmodule identifies the memory device for reprovisioning when the memorydevice usable memory life age indicator is 3 years and 1 day and ausable memory life age threshold associated with the memory device is 3years.

The method continues at step 142 where the processing module extractsdata from the memory device. Such extraction includes at least one ofretrieving at least a portion of the data from the memory device,sending a data retrieval message to the memory device, sending a dataretrieval message to a legacy computing system associated with thememory device, sending a data retrieval message to a DS unit associatedwith the memory device, and receiving the data from the memory device.

The method continues at step 144 where the processing modulereprovisions the memory device from the legacy storage protocol to adispersed storage error coding storage protocol. The reprovisioning thememory device includes one or more of integrating the memory device intoa dispersed storage network (DSN) memory (e.g., detecting activation ofthe memory device in the DSN memory), establishing a local storage tablethat indicates a mapping of slice names to memory device addresseswithin the DSN memory, writing a plurality of zeros to the memorydevice, writing a plurality of ones to the memory device, writing asequence of a plurality of zeros and ones to the memory device, writingrandom data to the memory device, and verifying that performance of thememory device within the DSN memory is in accordance with a dispersedstorage error coding storage protocol (e.g., compare data written todata read, test portions of the memory device).

Alternatively, or in addition to, the reprovisioning the memory devicefurther includes at least one of converting the data extracted from thememory device from the legacy storage protocol to the dispersed storageerror coding storage protocol to produce dispersed storage error encodeddata (e.g., slices) and storing at least a portion of the dispersedstorage error encoded data in the DSN memory in accordance with thedispersed storage error coding storage protocol.

Alternatively, or in addition to, the reprovisioning the memory devicefurther includes determining a memory device usability level of thememory device and reprovisioning the memory device into the DSN memoryin accordance with the memory device usability level. The memory deviceusability level includes at least one of a data retrieval failure rate,a memory element failure (e.g., a bad disk sector), a mechanical diskoperational issue, and a data write verification issue. For example,processing module reprovisions the memory device into the DSN memory byupdating the local storage table to indicate a mapping of slice namesassociated with slices requiring a storage reliability level consistentwith the memory device usability level to memory device addresses withinthe memory device.

FIG. 9A is a schematic block diagram of an embodiment of a dispersedstorage (DS) unit 36. The DS unit 36 includes a plurality of memories1_1 to M_N, and a memory control module 146. The DS unit 36 may beimplemented with any number of memories. The memories 1_1 to M_N may bephysically repurposed to the DS unit from a legacy computing system. Thememory control module 146 may be implemented utilizing a computing core26. The memory control module 146 is operably coupled to each of theplurality of memories 1_1 to M_N. The memory control module 146functions include one or more of controlling the memories, storing data,retrieving data, deleting data, listing data, configuring memories,allocating memories, determining status, storing metadata, storingencryption keys, storing memory device access information, and managingmemories. The memory control module 146 interfaces to the network 24 tofacilitate communication of control information 148 and slices 11 with adispersed storage network (DSN).

In an example of operation, the memory control module 146 receivesslices 11 via the network 24. The memory control module 146 selects oneor more of the memories 1_1 to M_N to produce selected memories to storethe slices 11 based on one or more of a vault identifier, a useridentifier, a data identifier, a current allocation of memories tovaults, memory status, a memory age indicator, an error message, amemory performance history record, and a storage requirement. The memorycontrol module 146 stores the slices in the selected memories.

As another example of operation, the memory control module 146determines a memory status of a memory based on one or more of a query,a test, a performance record, an availability record, a reliabilityrecord, an error message, a memory age indicator, a usable memory lifeindicator, a set of usable memory life thresholds, a previous memorystatus, a message, a usable portion of the memory indicator, an unusableportion of the memory indicator, and a command. For instance, the memorycontrol module 146 determines the memory status based on verifyingoperation via a test of one or more portions of the memory. The methodof operation of the memory control module 146 is discussed in greaterdetail with reference to FIG. 9B-24 .

FIG. 9B is a table illustrating an example of a memory assignment table150. The memory assignment table 150 includes a memory identifier (ID)field 152, an allocation field 154, and a memory status field 156. Thememory ID field 152 includes memory ID entries that list an identifierassociated with a particular memory such that substantially all memoriesof a dispersed storage (DS) unit are listed within the memory assignmenttable 150 (e.g., memories 1_1 to M_N).

The allocation field 154 includes allocation entries that indicatewhether a memory of an associated memory ID is unallocated forutilization or allocated for utilization to a vault of a dispersedstorage network (DSN). For example, memories 1_1, 2_2, M_2, and M_N areunallocated, memory 1_2 is allocated to vault 320, memory 1_N isallocated to vault 59B, memories 2_1 and 2_N are allocated to vault 10A,and memory M_1 is allocated to vault 457. Two or more memories may beallocated to the same vault when the two or more memories are utilizedto store slices of two or more pillars. Two or more memories may beallocated to the same vault when the two or more memories are utilizedto store sub-slices of a slice received via the network 24.

The memory status field 156 includes memory status entries that indicatea memory status of an associated memory. For example, memory 1_1 has alevel 3 memory status, memory 1_2 as a level 1 memory status, memory 1_Nhas a level 2 memory status, memory 2_1 has the level 1 memory status,memory 2_2 as an unusable memory status, memory 2_N has the level 2memory status, memory M_1 as the level 1 memory status, memory M_2 asthe unusable memory status, and memory M_N has the level 1 memorystatus.

FIG. 10A is a flowchart illustrating an example of adding a memory. Themethod begins with step 158 where a processing module (e.g., of a memorycontrol module) detects addition of a memory. The detection may be basedon one or more of a network management message, a query, a test, a userinput, an error message, a configuration message, and available memorymessage, a memory card insertion detector output, a message, and acommand. The method continues at step 160 where the processing moduledetermines memory status of the memory (e.g., as discussed withreference to FIG. 9A). The method continues at step 162 where theprocessing module updates a memory assignment table to indicate thememory status for the corresponding memory.

FIG. 10B is a flowchart illustrating an example of allocating memory,which includes similar steps to FIG. 10A. The method begins with step164 where a processing module (e.g., a memory control module) determinesa memory allocation needs change. The determination may be based on oneor more of an error message, an error rate indicator, a comparison ofthe error rate indicator to an error rate threshold, a test, a query, amessage, and a command. For example, the processing module determinesthat the memory allocation needs change when the error rate indicator isabove the error rate threshold.

The method continues at step 166 where the processing module determinesmemory requirements (e.g., which memory status level is required). Thedetermination may be based on one or more of a memory requirementindicator, a data type, stored data, a data frequency of accessindicator, a previous memory status level, a message, and a command. Forexample, the processing module determines the memory requirements basedon the previous memory status level. Alternatively, the current memorystatus level may have risen above the current memory status level. Forexample, the processing module determines the memory requirements asmemory status level 2 when the previous memory status level is 2 and thecurrent memory status level is 3.

The method continues at step 168 where the processing module determinesa memory status of a candidate memory. The determination may be based ona lookup of a memory assignment table, a refresh query, a message, and acommand. For example, the processing module determines the memory statusof the candidate memory by reading a memory status field entry for thememory from the memory assignment table. The method continues at step170 where the processing module determines whether the candidate memorysatisfies the memory requirements based on comparing the two. Forexample, the processing module determines that the candidate memorysatisfies the memory requirements when the memory status of thecandidate memory is level 1 or 2, and the memory requirements is memorystatus level 2. As another example, the processing module determinesthat the candidate memory does not satisfy the memory requirements whenthe memory status of the candidate memory is level 3. The methodcontinues to step 172 when the processing module determines that thecandidate memory satisfies the memory requirements. The method repeatsback to step 168 when the processing module determines that thecandidate memory does not satisfy the memory requirements.

The method continues at step 172 where the processing module allocatesthe memory by assigning the memory to a vault (e.g., a vault in need ofstorage capacity) and configuring the memory. The method continues atstep 162 of FIG. 10A where the processing module updates a memoryassignment table (e.g., indicating which vault is assigned to the memoryand the current memory status level).

FIG. 11A is a flowchart illustrating an example of storing an encodeddata slice. The method begins with step 176 where a processing module(e.g., of a memory control module) receives a slice storage request. Therequest may include one or more of a slice, a slice name, a vaultidentifier, a source name, and storage requirements. The methodcontinues at step 178 where the processing module determines whether tosub-slice the slice. The determination may be based on one or more ofthe slice, the slice name, the vault identifier, the source name, thestorage requirements, a predetermination, a lookup, a message, a datatype indicator, a command, a memory assignment table, and a comparisonof the storage requirements to a memory status of a memory. For example,the processing module determines to not sub-slice the slice when storagerequirements are exceeded by a memory status of a memory associated withthe vault as indicated in the memory assignment table. The methodbranches to step 182 when the processing module determines to sub-slicethe slice. The method continues to step 180 when the processing moduledetermines not to sub-slice the slice. The method continues at step 180where the processing module stores the slice in a memory associated withthe vault as indicated by the memory assignment table.

The method continues at step 182 where the processing module determinesan internal memory storage set when the processing module determines tosub-slice the slice. The internal memory storage set includes memoriesassociated with a common dispersed (DS) unit. The determination may bebased on one or more of the slice, the slice name, the vault identifier,the source name, the storage requirements, a predetermination, a datatype indicator, a lookup, a message, a command, the memory assignmenttable, and a comparison of the storage requirements to a memory statusof a memory. For example, the processing module determines the internalmemory storage set to be a plurality of memories that have a memorystatus level that is favorable as compared to the storage requirements.Note that the memory status level of the plurality of memories may beless stringent than the storage requirements when storing the slice andjust one memory. For instance, the processing module determines theinternal memory storage set to be a plurality of memories, each of whichhas a memory status level of 3 when the storage requirements require amemory status level 2. Note that the requirements are substantially metbased on the nature of the error coded dispersal storage functionutilized to produce sub-slices from the slice to store in the pluralityof memories.

The method continues at step 184 where the processing module encodes theslice utilizing the error coded dispersal storage function to producesub-slices. The sub-slices include one or more sets of sub-slices. Themethod continues at step 186 where the processing module stores thesub-slices in the internal memory storage set. The method continues atstep 188 where the processing module updates a local virtual-dispersedstorage network (DSN)-to-physical-memory location table indicating whichsub-slices (e.g., which pillars) are stored in which memories of theinternal memory storage set.

FIG. 11B is a flowchart illustrating an example of retrieving an encodeddata slice, which includes similar steps to FIG. 11A. The method beginswith step 176 of FIG. 11A where a processing module (e.g., of a memorycontrol module) receives a slice retrieval request from a requestingentity. The request may include one or more of a slice name, a vaultidentifier, a source name, and storage requirements. The methodcontinues at step 190 where the processing module determines whether theslice was sub-sliced prior to being stored. The determination may bebased on one or more of a lookup in a virtual-as per storage network(DSN)-to-physical-memory location table, a memory assignment tablelookup, the vault identifier, the slice and, the source name, storagerequirements, a message, and a command. For example, the processingmodule determines that the slice was sub-sliced when thevirtual-DSN-to-physical-memory location table indicates memories of aninternal memory storage set where sub-slices were previously stored forthe slice. The method branches to step 182 of FIG. 11A when theprocessing module determines that the slice was sub-sliced. The methodcontinues to step 192 when the processing module determines that theslice was not sub-sliced. The method continues at step 192 where theprocessing module retrieves the slice from a memory as indicated by amemory assignment table lookup (e.g., the memory associated with a vaultassociated with the slice).

The method continues at step 182 of FIG. 11A where the processing moduledetermines the internal memory storage set when the processing moduledetermines that the slice was sub-sliced. The method continues at step194 where the processing module retrieves the sub-slices from theinternal memory storage set. The method continues at step 196 where theprocessing module decodes the sub slices utilizing an error codeddispersal storage function to produce the slice. The method continues atstep 198 where the processing module sends the slice to the requestingentity.

FIG. 12 is a flowchart illustrating another example of allocatingmemory. The method begins with step 200 where a processing module (e.g.,of a memory control module) determines a memory to analyze. Thedetermination may be based on one or more of an error message, where ananalysis process left off last time, a message, and a command. Themethod continues at step 160 of FIG. 10A where the processing moduledetermines a current memory status for the memory.

The method continues at step 202 where the processing module determineswhether the current memory status is different than a stored memorystatus (e.g., a previous memory status). For example, the processingmodule compares the current memory status to the stored memory statusfrom a memory assignment table lookup. The method branches to step 204when the processing module determines that the current memory status isdifferent than the stored memory status. The method repeats back to step200 when the processing module determines that the current memory statusis not different than the stored memory status.

The method continues at step 204 where the processing module allocates asecond memory by assigning one of a plurality of candidate memories(e.g., usable at a memory status level that meets the requirements setby the stored memory status) to be associated with a vault associatedwith the memory (e.g., a vault in need of a memory that meets therequired memory status level). In addition, the processing module mayconfigure the second memory.

The method continues at step 206 where the processing module movesslices from the memory to the second memory wherein the moving includesone or more of retrieving the slice from the memory and storing theslice in the second memory, retrieving the slice from the memory andstoring sub-slices in the second memory produced from the slice,retrieving sub-slices from the memory and storing the sub-slices in thesecond memory, and retrieving sub-slices from the memory and storingre-encoded sub-slices in the second memory produced from the sub-slices.The method continues with step 162 of FIG. 10A for the processing moduleupdates the memory assignment table indicating which vault is assignedto the memory and the current memory status level. The method todetermine an approach to move slices is discussed in greater detail withreference to FIG. 13 .

FIG. 13A is a flowchart illustrating an example of migrating a pluralityof encoded data slices. The method begins with step 208 where aprocessing module (e.g., of a memory control module) monitors areprovisioned memory device that has been reprovisioned from a legacystorage protocol to an error coding dispersed storage protocol. Themethod continues at step 210 where the processing module determineswhether a usable memory life of the reprovisioned memory device in theerror coding dispersed storage protocol has expired. The processingmodule determines the usable memory life by at least one of querying amemory usability level table, testing the reprovisioned memory device,determining a memory assignment, receiving an error message, retrievingan error message history, receiving a message, obtaining historicalreliability data of similar reprovisioned memory devices, areprovisioned memory device age, a reprovisioned memory type, areprovisioned memory usage level, and receiving a command. Theprocessing module determines whether the usable memory life has expiredbased on one or more of a network management message, a reprovisionedmemory device usable memory life age indicator, a usable memory life agethreshold, a user input, an error message, a configuration message, areplacement schedule, an available memory message, a memory deviceinsertion detector output, a message, and a command. For example, theprocessing module determines that the usable memory life has expiredwhen the reprovisioned memory device usable memory life age indicator is4 years and 1 day and a usable memory life age threshold associated withthe reprovisioned memory device is 4 years.

The method branches to step 212 when the processing module determinesthat the usable memory life of the reprovisioned memory device hasexpired. The method repeats back to step 208 when the processing moduledetermines that the usable memory life of the reprovisioned memorydevice has not expired. The method continues at step 212 where theprocessing module determines a data migration scheme for migrating aplurality of encoded data slices stored on the reprovisioned memorydevice. The data migration scheme includes at least one of a datatransfer scheme, sub-slicing data migration for an encoded data slice ofthe plurality of encoded data slices, pillar width expansion (e.g.,generating one or more slices corresponding to one or more additionalpillars while maintaining a constant decode threshold), and rebuildingan encoded data slice of the plurality of encoded data slices. Theprocessing module determines the data migration scheme based on one ormore of a usable memory life of each of one or more other memorydevices, a storage requirement, querying a memory usability level table,testing at least one memory device of the one or more memory devices,determining a memory assignment, receiving an error message, retrievingan error message history, receiving a message, and receiving a command.

For example, the processing module determines the data migration schemeto be the data transfer scheme when at least one of the one or moreother memory devices is associated with a usable memory life thatcompares favorably to the storage requirement. As another example, theprocessing module determines the data migration scheme to be sub-slicingdata migration for the encoded data slice of the plurality of encodeddata slices when none of the one or more other memory devices isassociated with the usable memory life that compares favorably to thestorage requirement. As yet another example, the processing moduledetermines the data migration scheme to be rebuilding the encoded dataslice when a encoded data slice error is detected (e.g., a calculatedslice integrity indicator compares unfavorably to a recovered sliceintegrity indicator, a missing slice condition is detected).Alternatively, or in addition to, the processing module determines thedata migration scheme by determining useful memory life indications ofthe one or more other devices and selecting the data migration schemebased on the useful memory life indications of the one or more otherdevices.

The method continues at step 214 where the processing module migratesthe plurality of encoded data slices from the reprovisioned memorydevice to one or more other memory devices in accordance with the datamigration scheme. For example, the processing module selects a memorydevice of the one or more other memory devices and transfers theplurality of encoded data slices to the memory device when the datamigration scheme is the data transfer scheme. As another example, theprocessing module dispersed storage error encodes the encoded data sliceto produce a set of encoded sub-slices, selects a set of memory devicesof the one or more other memory devices, and sends the set of encodedsub-slices to the set of memory devices when the data migration schemeis the sub-slicing data migration for the encoded data slice of theplurality of encoded data slices. As yet another example, the processingmodule retrieves at least a decode threshold number of encoded dataslices associated with the encoded data slice, reconstructs a datasegment from the decode threshold number of encoded data slices,dispersed storage error encodes the data segment to produce a set ofrebuilt encoded data slices, selects a rebuilt encoded data slice of theset of rebuilt encoded data slices, selects a memory device of the oneor more other memory devices, and sends the rebuilt encoded data sliceto the memory device when the data migration scheme is the rebuildingthe encoded data slice of the plurality of encoded data slices.

Alternatively, or in addition to, the processing module migrates theplurality of encoded data slices further by determining storagerequirements for the plurality of encoded data slices, determining thatthe one or more other memory devices satisfies the storage requirements,and when the one or more other memory devices satisfies the storagerequirements, enabling the migrating of the plurality of encoded dataslices from the reprovisioned memory device to the one or more othermemory devices.

FIG. 13B is a flowchart illustrating an example of migrating an encodeddata slice. The method begins with step 216 where a processing module(e.g., of a memory control module) determines a usable memory lifeindication of a reprovisioned memory device operable in accordance withan error coding dispersed storage protocol, wherein the reprovisionedmemory device has been reprovisioned from a legacy storage protocol tothe error coding dispersed storage protocol. The processing moduledetermines the usable memory life indication by at least one of queryinga memory usability level table regarding a portion of the reprovisionedmemory device storing the encoded data slice, testing the portion of thereprovisioned memory device, determining a memory assignment regardingthe portion, receiving an error message regarding the portion,retrieving an error message history regarding the portion, receiving amessage regarding the portion, and receiving a command regarding theportion. For example, processing module determines the usable memorylife indication by retrieving the error message history regarding theportion by obtaining historical reliability data of similarreprovisioned memory devices, memory usage levels, and memory age.

The method continues at step 218 where the processing module determineswhether to migrate an encoded data slice of a plurality of encoded dataslices to one or more other memory devices based on the usable memorylife indication. For example, the processing module determines tomigrate the encoded data slice when the usable memory life indicationcompares unfavorably to a storage requirement associated with theencoded data slice. The method branches to step 220 when the processingmodule determines to migrate the encoded data slice. The method repeatsback to step 216 when the processing module determines not to migratethe encoded data slice.

The method continues at step 220 where the processing module determinesa migration scheme. The migration scheme includes at least one of a datatransfer scheme, sub-slicing data migration, pillar width expansion(e.g., generating one or more slices corresponding to one or moreadditional pillars while maintaining a constant decode threshold), andrebuilding the encoded data slice. The processing module determines themigration scheme based on one or more of a usable memory life of each ofone or more other memory devices, a storage requirement, querying amemory usability level table, testing at least one memory device of theone or more memory devices, determining a memory assignment, receivingan error message, retrieving an error message history, receiving amessage, and receiving a command.

For example, the processing module determines the migration scheme to bethe data transfer scheme when at least one of the one or more othermemory devices is associated with a usable memory life that comparesfavorably to the storage requirement. As another example, the processingmodule determines the migration scheme to be sub-slicing data migrationfor the encoded data slice when none of the one or more other memorydevices is associated with the usable memory life that comparesfavorably to the storage requirement. As yet another example, theprocessing module determines the migration scheme to be rebuilding theencoded data slice when an encoded data slice error is detected.

The method continues at step 222 where the processing module migratesthe encoded data slice to the one or more other memory devices inaccordance with the migration scheme. For example, the processing moduleselects a memory device of the one or more other memory devices andtransfers the encoded data slice to the memory device when the migrationscheme is the data transfer scheme. As another example, the processingmodule dispersed storage error encodes the encoded data slice to producea set of encoded sub-slices, selects a set of memory devices of the oneor more other memory devices, and sends the set of encoded sub-slices tothe set of memory devices when the migration scheme is the sub-slicingdata migration. As yet another example, the processing module retrievesat least a decode threshold number of encoded data slices associatedwith the encoded data slice, reconstructs a data segment from the decodethreshold number of encoded data slices, dispersed storage error encodesthe data segment to produce a set of rebuilt encoded data slices,selects a rebuilt encoded data slice of the set of rebuilt encoded dataslices, selects a memory device of the one or more other memory devices,and sends the rebuilt encoded data slice to the memory device when themigration scheme is the rebuilding the encoded data slice.

FIG. 14 is a flowchart illustrating another example of allocatingmemory, which includes similar steps to FIGS. 10A and 12 . The methodbegins with step 200 of FIG. 12 where a processing module (e.g., of amemory control module) determines a current memory to analyze.

The method continues at step 224 where the processing module determinesa current memory utilization for the memory. The determination may bebased on one or more of a memory status table, a test, a memory capacityindicator, a memory use indicator, a memory assignment table, a memoryquery, an error message, an error message history, a message, and acommand. For example, the processing module determines the currentmemory utilization by a memory status table lookup.

The method continues at step 226 where the processing module determinesalternative memories that have a memory status that substantially meetsstorage requirements of the memory. The determination may be based onone or more of a memory assignment table, a memory status level of thecurrent memory, a memory status level of a candidate alternative memory,a comparison of the memory status level of the candidate alternativememory to the memory status level of the current memory, apredetermination, a lookup, a message, and a command. For example, theprocessing module determines that candidate alternative memory 2_1 hasmemory status level 1 and the current memory 1_2 as a memory statuslevel 1.

The method continues at step 228 where the processing module determineswhether to move slices from the current memory to an alternative memoryof the alternative memories. The determination may be based on one ormore of the alternative memories, the current memory utilization, anavailable memory indicator of the candidate memory, a predetermination,and lookup, a message, and a command. For example, the processing moduledetermines to move the slices from the current memory to the alternativememory when the available memory indicator of the candidate memoryindicates that sufficient memory is available to store the amount ofcurrently stored slices as indicated by the current memory utilization.The method branches to step 230 when the processing module determines tomove slices from the current memory to the alternative memory. Themethod repeats back to step 200 of FIG. 12 when the processing moduledetermines not to move slices from the current memory to an alternativememory.

The method continues at step 230 where the processing module allocatesthe candidate alternate memory by assigning the alternate memory to beassociated with a vault associated with the current memory. In addition,the processing module may configure the alternate memory as previouslydiscussed. The method continues at step 232 where the processing modulemoves slices from the current memory to the alternate memory, whereinthe moving may include one or more of retrieving the slice from thecurrent memory and storing the slice in the alternate memory, retrievingthe slice from the current memory and storing sub-slices in the ultimatememory produced from the slice, retrieving sub-slices from the currentmemory and storing the sub-slices in the alternate memory, andretrieving sub-slices from the current memory and storing re-encodedsub-slices in the alternate memory produced from the sub-slices. Themethod continues at step 234 where the processing module powers down thecurrent memory to save power since it is not required. The methodcontinues at step 162 of FIG. 10A where the processing module updates amemory assignment table indicating which vault is assigned to thealternate memory and that the current memory status is powered down.

FIG. 15 is a flowchart illustrating another example of allocatingmemory, which includes similar steps to FIG. 10A. The method begins withstep 236 where a processing module (e.g., of a memory control module)determines a current memory status of each of a plurality of memories,wherein the determination of the memory status is as previouslydiscussed (e.g., a lookup in a memory assignment table, a test, a query,etc.). The method continues at step 238 where the processing moduledetermines a weighted current memory status for the plurality ofmemories. For example, the processing module determines the weightedcurrent memory status by calculating an average memory status level forthe aggregate of the plurality of memories. As another example, theprocessing module determines the weighted current memory status bymultiplying each memory status level by an associated weighting factorto produce weighted memory status levels and then averaging the weightedmemory status levels to produce the weighted current memory status.

The method continues at step 240 where the processing module determineswhether the weighted current memory status compares favorably to astatus threshold. For example, the processing module determines that theweighted current memory status compares favorably to the statusthreshold when the weighted current memory status is less than thestatus threshold. The method branches to step 242 when the processingmodule determines that the weighted current memory status does notcompare favorably to the status threshold. The method repeats back tostep 236 when the processing module determines that the weighted currentmemory status compares favorably to the status threshold.

The method continues at step 242 where the processing module allocatesan alternative plurality of memories. For example, the processing moduleallocates the alternative plurality of memories when the alternativeplurality of memories is idle (e.g., not allocated to a vault). Such anallocation has been previously discussed.

The method continues at step 244 where the processing module establishesan additional pillar in an error coding dispersal storage functionutilized to encode data into slices. For example, processing module addsa 17th pillar to the error coding dispersal storage function that waspreviously utilizing 16 pillars. The processing module retrieves adecode threshold number of slices from other dispersal storage (DS)units, decodes the decode threshold number of slices to produce data,encodes the data utilizing the error coding dispersal storage functionwith the additional pillar to produce new slices including slices of theadditional pillar. The processing module stores the slices of theadditional pillar in the alternate plurality of memories. Note that thedata may be recovered by retrieving a decode threshold number of slicesincluding slices from the current memory and slices from the alternatememory. The method continues with step 162 of FIG. 10A where theprocessing module updates a memory assignment table indicating whichmemories are associated with which vaults and which memories may remainun-allocated. The method continues at step 246 where the processingmodule updates a virtual disperse towards network (DSN) to physicallocation table to map the alternate plurality of memories of a DS unitto new pillars of every vault.

FIG. 16 is a flowchart illustrating another example of allocatingmemory, which includes similar steps to FIGS. 10A and 15 . The methodbegins with steps 236-242 of FIG. 15 where a processing module (e.g., ofa memory control module) determines a current memory status of each of aplurality of memories, determines a weighted current memory status forthe plurality of memories, determines whether the weighted currentmemory status compares favorably to a status threshold, and allocates analternate plurality of memories when the processing module determinesthat the weighted current memory status compares unfavorably to thestatus threshold.

The method continues at step 248 where the processing module move slicesfrom the plurality of memories to an alternate plurality of memories.For example, the processing module moves the slices directly byretrieving the slices from the plurality of memories and storing theslices in the alternate plurality of memories. As another example, theprocessing module moves the slices indirectly by retrieving the slicesfrom the plurality of memories, temporarily storing the slices in atemporary memory, retrieving the slices from the temporary memory, andstoring slices in the alternate plurality of memories. The methodcontinues with step 162 of FIG. 10A where the processing module updatesa memory assignment table. The method continues with step 246 of FIG. 15where the processing module updates a virtual dispersed storage network(DSN) to physical location table.

FIG. 17 is a flowchart illustrating an example of migrating a memory.The method begins with step 250 where a processing module (e.g., of amemory control module) determines whether to migrate a memory. Thedetermination may be based on one or more of comparing a memory statusto a migration threshold, a migration profile, a lookup, apredetermination, a schedule, a query, a message, and a command. Forexample, the processing module determines to migrate the memory when thememory status is above the migration threshold. As another example, theprocessing module determines to migrate the memory when a scheduleindicates that it is time to migrate the memory (e.g., a magnetic harddisk drive memory is 37 months old). The method branches to step 252when the processing module determines to migrate the memory. The methodrepeats back to step 250 when the processing module determines not tomigrate the memory.

The method continues at step 252 where the processing module retrievesdata from the memory. The method continues at step 254 where theprocessing module saves the data as temporary data (e.g., as data in atemporary memory and/or as encoded data slices in a dispersed storagenetwork memory). The method continues at step 256 where the processingmodule detects installation of the memory in a dispersed storage network(DSN) memory. For example, the memory is physically moved from a legacycomputing system to the DSN memory. As another example, the memory isphysically moved from another DSN memory to the DSN memory. Thedetection may be based on one or more of reading data from the memoryand comparing the data to the temporary data, a network managementmessage, a user input, an error message, a configuration message, anavailable memory message, a memory card insertion detector output, amessage, and a command.

The method continues at step 258 where the processing module configuresthe memory for operation within the DSN memory. For example, theprocessing module configures the memory by writing zeros to the memory.As another example, the processing module configures the memory bywriting ones to the memory. As yet another example, the processingmodule configures the memory by writing random data to the memory. Theprocessing module may perform several such cycles of writing data to thememory to complete the configuration step. The processing module maydetermine the memory status of the memory including the determination ofusable portions (e.g., operational magnetic hard disk drive sectors) andunusable portions of the memory. The processing module utilizes thememory to store subsequent encoded data slices in the memory.

The method continues at step 260 where the processing module determinesstorage requirements. The determination may be based on one or more ofthe temporary data, a data size indicator, a security indicator, aperformance indicator, an availability indicator, a lookup, a message,and a command. The method continues at step 262 where the processingmodule encodes the temporary data utilizing an error coding dispersalstorage function to produce a plurality of sets of encoded data slices.The method continues at step 264 where the processing module outputs theplurality of sets of encoded data slices to a dispersed storage network(DSN) memory for storage therein. At least some of the encoded dataslices may be stored in the memory.

FIG. 18 is a flowchart illustrating an example of securely storing data.The method begins at step 266 where a processing module (e.g., of amemory control module) receives data to store. The data may include oneor more of a data object, a data segment, and one or more data slices.The method continues at step 268 where the processing module determinesan encryption key. The determination may be based on one or more of anoutput of a random number generator, a lookup, a predetermination, amessage, a received key, and a command. The method continues at step 270where the processing module encrypts the data utilizing the encryptionkey and in accordance with an encryption function to produce encrypteddata. The method continues at step 272 where the processing moduleencodes the encryption key utilizing an error coding dispersal storagefunction to produce encoded key slices. The method continues at step 274where the processing module deletes the encryption key.

The method continues at step 276 where the processing module encodes theencrypted data utilizing the error coding dispersal storage function toproduce encoded data slices. Alternatively, the processing module maydetermine not to encode the encrypted data based on one or more of asecurity requirement, a memory availability indicator, a lookup, amessage, and a command. For example, the processing module determinesnot to encode the encrypted data when a memory availability indicator isbelow an availability threshold. The method continues at step 278 wherethe processing module outputs the encoded key slices and the encodeddata slices to a plurality of memories for storage therein. For example,the slices are stored in memories wherein the memories are within acommon dispersed storage (DS) unit. The processing module outputs theencrypted data to the plurality of memories when the processing moduledetermines not to encode the encrypted data as previously discussed. Theprocessing module stores memory locations of where the encoded keyslices and the encoded data slices are stored.

In a retrieval example of operation, the processing module retrieves theencoded key slices and decodes the encoded key slices in accordance withthe error coding dispersal storage function to produce the encryptionkey. The processing module retrieves the encoded data slices and decodesthe encoded data slices in accordance with the error coding dispersalstorage function to produce the encrypted data. Next, the processingmodule decrypts the encrypted data utilizing the encryption key and inaccordance with a decryption function to reproduce the data.

FIG. 19 is a flowchart illustrating an example of storing data, whichincludes similar steps to FIG. 17 . The method begins with step 280where a processing module (e.g., of a memory control module) receives arequest to store data as slices. The request may include one or more ofa storage request, data, a slice, a slice name, a source name, a vaultidentifier (ID), and storage requirements. The processing module mayreceive the data by receiving the data (e.g. via a network interface) orby retrieving the data from a memory (e.g., a memory within a dispersedstorage (DS) unit). The method continues at step 281 where theprocessing module determines storage requirements. The storagerequirements may include one or more requirements of performance,reliability, availability, security, duration storage, estimatedretrieval frequency, and class (e.g., enterprise, desktop, near-line).The determination may be based on one or more of the data, a data type,a reliability indicator, a security indicator, an estimated retrievalfrequency indicator, a class of storage indicator, a lookup, a request,a query, a predetermination, and a command.

The method continues at step 282 where the processing module determinesa plurality of candidate memories. The determination may be based on oneor more of a memory assignment table, a query, a lookup, apredetermination, the data, a data identifier, a vault ID, and acommand. The method continues at step 284 where the processing moduledetermines characteristics of each of the memories of the plurality ofcandidate memories, wherein the characteristics includes one or more oferror history, sector errors, catastrophic failure history, speed,capability, utilization, available memory, age, number of bad memoryblocks, unassigned sectors, spare sectors, a disk drive model, a diskdrive manufacturer, and a class. The determination may be based on oneor more of a memory assignment table, a lookup, a query, a test, amessage, and a command. For example, the processing module determinesthat a memory of the plurality of candidate memories has bad memoryblocks in 50% of the memory based on a test.

The method continues at step 286 where the processing module determineserror coding dispersal storage function parameters. The determinationmay be based on one or more of the storage requirements, thecharacteristics of each of the memories of the plurality of candidatememories, the candidate memories, a reliability policy, an errormessage, a lookup, a predetermination, a message, and a command. Themethod continues at step 288 where the processing module determines aninternal memory storage set. The determination may be based on one ormore of the storage requirements, the characteristics, the candidatememories, the error coding dispersal storage function parameters, andavailability of the candidate memories.

The method continues at step 290 where the processing module encodes thedata utilizing an error coding dispersal storage function in accordancewith the error coding dispersal storage function parameters to produceencoded data slices. The method continues at step 292 where theprocessing module stores the encoded data slices in the internal memorystorage set. The method continues at step 246 of FIG. 15 where theprocessing module updates a virtual dispersed storage network (DSN) tophysical memory location table. In addition, the processing module mayupdate a memory assignment table with a mapping of vaults to memories.

FIG. 20 is a flowchart illustrating an example of converting legacy datato dispersed data. The method begins with step 294 where a processingmodule (e.g., of a memory control module) retrieves data (e.g. legacydata that may not be in the form of encoded data slices) from a memoryof a plurality of memories. For example, the memory may include a legacymemory in a legacy memory unit that contains a plurality of legacymemories each of which may be currently utilized to store legacy data.The method continues at step 296 where the processing module identifiesavailable storage space of the plurality of memories. Available memoryspace includes memory that is unallocated and operable. Theidentification may be based on one or more of a query, a test, a memorystatus table, a lookup, a message, and a command.

The method continues at step 298 where the processing module encodes thedata utilizing an error coding dispersal storage function to produce aplurality of sets of encoded data slices. The method continues at step300 where the processing module stores the plurality of sets of encodeddata slices in the available storage space of the plurality of memories.For example, the processing module stores the slices all in the memory(e.g., the same memory where the data was stored). As another example,the processing module stores all the slices in another memory. As yetanother example, the processing module stores the slices in two or moreof the memories.

The method continues at step 302 where the processing module deletes thedata from the memory of the plurality of memories. In addition, theprocessing module deletes copies of the data from other memories of theplurality memories when other copies of the data exist. Note that animprovement to the system is provided by deleting the other copies ofthe data by freeing up more memory capacity to be utilized in thesubsequent storage of more encoded data slices produced from stillfurther data.

FIG. 21A is a flowchart illustrating another example of convertinglegacy data to dispersed data. The method begins at step 304 whereprocessing module (e.g., of a memory control module) identifies a set ofstored files that includes an original file and one or more back-upcopies of the original file. The original file includes one or more of adata object and a data block. The identifying the set of stored filesincludes at least one of determining content of the one or more back-upcopies substantially matches content of the original file, determining afunction-based indicator (e.g., a hash digest, a deterministic functionoutput, a mask generating function output) of the one or more back-upcopies substantially matches a function-based indicator of the originalfile, determining a back-up indicator of the one or more back-up copiessubstantially identifies the original file, and determining a back-upindicator of the original file identifies the one or more back-upcopies.

The method continues at step 306 where the processing module dispersedstorage error encodes one of the set of stored files using a first setof dispersed storage error coding parameters to produce a plurality ofsets of temporary encoded data slices. For example, uses a first set ofdispersed storage error coding parameters that includes a pillar widthof 8 and a decode threshold of 6 to produce the plurality sets oftemporary encoded data slices such that a blowup factor is only8/6=1.33.

The method continues at step 308 where the processing module temporarilystores the plurality of sets of temporary encoded data slices. Forexample, the processing module temporarily stores the plurality of setsof temporary encoded data slices in a memory that stores at least one ofthe one or more backup copies of the original file by overwriting the atleast one of the one or more backup copies of the original file with theplurality of sets of temporary encoded data slices.

The method continues at step 310 where the processing module commencesto facilitate deletion of the set of stored files after storage of theplurality of sets of temporary encoded data slices. The deleting the setof stored files includes at least one of immediately deleting the set ofstored files and verifying storage of a plurality of sets of encodeddata slices prior to deleting the set of stored files. For example, theprocessing module immediately deletes the set of stored files when theprocessing module successfully temporarily stores the plurality of setsof temporary encoded data slices. As another example, the processingmodule continues the method, as described below, to create and store theplurality of sets of encoded data slices prior to deleting the set ofstored files when the processing module does not successfullytemporarily store the plurality of sets of temporary encoded dataslices.

The method continues at step 312 where the processing module dispersedstorage error encodes a one of the set of stored files to produce theplurality of sets of encoded data slices. For example, the processingmodule retrieves the plurality of sets of temporary encoded data slices,dispersed storage error decodes the plurality of sets of temporaryencoded data slices to reproduce the original file, and dispersedstorage error encodes the original file to produce the plurality of setsof encoded data slices when the one of a set of stored files is notavailable. As another example, the processing module dispersed storageerror encodes the one of the set of stored files to produce theplurality of sets of encoded data slices when the one of the set ofstored files is available.

The method continues at step 314 where the processing module facilitatesstorage of the plurality of sets of encoded data slices in the memory asmemory becomes available due to the deleting of the set of stored files.The facilitating storage of the plurality of sets of encoded data slicesincludes overwriting a back-up copy of the one or more back-up copieswith at least some of the plurality of sets of encoded data slices andwriting some other encoded data slices of the plurality of sets ofencoded data slices to the memory that stores the plurality of sets oftemporary encoded data slices. The method continues at step 316 wherethe processing module deletes the plurality of sets of temporary encodeddata slices after storage of the plurality of sets of encoded dataslices.

FIG. 21B is a flowchart illustrating another example of convertinglegacy data to dispersed data. The method begins at step 318 where aprocessing module (e.g., of a memory control module) identifies a storedback-up file of a stored original file. The identifying the storedback-up file includes at least one of determining content of the storedback-up file substantially matches content of the stored original file,determining a function-based indicator of the stored back-up filesubstantially matches a function-based indicator of the stored originalfile, determining a back-up indicator of the stored back-up filesubstantially identifies the stored original file, and determining aback-up indicator of the stored original file identifies the storedback-up file.

The method continues at step 320 where the processing module facilitatesdeletion of the stored back-up file. The facilitation includes at leastone of writing at least one of zeros, ones, a random pattern, a dilutionpattern to a memory associated with storing the backup file and sendinga stored backup file deletion request (e.g., to the memory associatedwith the storing the backup file, to a file system).

The method continues at step 322 where the processing module dispersedstorage error encodes the stored original file to produce a plurality ofsets of encoded data slices. For example, the processing module utilizesa pillar width of 16 and a decode threshold of 10 to dispersed storageerror encode the stored original file to produce the plurality of setsof encoded data slices when long-term storage is desired.

The method continues at step 324 where the processing module facilitatesstorage of the plurality of sets of encoded data slices. Thefacilitating storage of the plurality of sets of encoded data slicesincludes at least one of overwriting the stored back-up file with atleast some of the plurality of sets of encoded data slices andoverwriting the stored original file with other encoded data slices ofthe plurality of sets of encoded data slices. The method continues atstep 326 where the processing module facilitates deletion of theoriginal file after verification of the storage of the plurality of setsof encoded data slices.

FIG. 22 is a flowchart illustrating an example of decommissioning amemory. The method begins with step 328 where a processing module (e.g.,of a memory control module) determines a memory status of a memory. Themethod continues at step 330 where the processing module determineswhether to decommission the memory. The determination may be based onone or more of comparing the memory status to a status threshold, anerror message, an error rate history, an error threshold, a message, anda command. For example, the processing module determines to decommissionthe memory when the memory status indicates an unusable state. Themethod branches to step 332 when the processing module determines todecommission the memory. The method repeats back step 328 when theprocessing module determines not to decommission the memory.

The method continues at step 332 where the processing module retrievesdata (e.g., encoded data slices) from the memory. The method continuesat step 334 where the processing module determines whether to re-slicethe data (e.g., encode slices into sub-slices). The determination may bebased on one or more of a memory status of one or more other memorieswithin a dispersed storage network (DSN), storage requirements, lookup,a message, and a command. For example, the processing module determinesto re-slice the data when a memory status level of each of a pluralityof candidate memories compares unfavorably to storage requirements. Themethod branches to step 338 when the processing module determines tore-slice the data. The method continues to step 336 when the processingmodule determines not to re-slice the data. The method continues at step336 where the processing module outputs the data to a dispersed storagenetwork memory for storage (e.g., the processing module transfersencoded data slices from the memory to other memories of the DSN). Themethod branches to step 342.

The method continues at step 338 where the processing module encodes thedata utilizing an error coding dispersal storage function to produce aplurality of sets of encoded data slices when the processing moduledetermines to re-slice the data. For example, the processing moduleproduces sub-slices for each slice. The method continues at step 340where the processing module outputs the plurality of sets of encodeddata slices to other memories of the DSN for storage therein. Forexample, the processing module outputs the plurality of sets of encodeddata slices to other memories within a common dispersed storage (DS)unit wherein the memory is also within the common DS unit. The methodcontinues at step 342 where the processing module decommissions thememory. For example, the processing module turns off the memory andupdates a memory assignment table to indicate that the memory isunusable.

FIG. 23A is a flowchart illustrating an example of securing legacy data.The method begins at step 344 where a processing module (e.g., a memorycontrol module) retrieves data from a memory to migrate. For example,the processing module retrieves legacy data from a legacy memory whereinthe legacy memory is a memory of a plurality of memories of a legacymemory unit. The method continues at step 346 where the processingmodule determines an encryption key (e.g., lookup, based on a randomnumber, based on a random seed, receiving). The method continues at step348 where the processing module encrypts the data utilizing theencryption key and in accordance with an encryption function to produceencrypted data.

The method continues at step 350 where the processing module stores theencrypted data in the memory. The method continues at step 352 where theprocessing module deletes the data from the memory leaving the encrypteddata intact in the memory. The method continues at step 354 where theprocessing module encodes the encryption key utilizing an error codingdispersal storage function to produce encoded key slices. The methodcontinues at step 356 where the processing module outputs the encodedkey slices to a plurality of memories for storage therein. For example,the plurality of memories is associated with the memory wherein theplurality of memories and the memory are part of a legacy memory unit.The method continues at step 358 where the processing module deletes theencryption key. In addition, the processing module may store memorylocations associated with the storing of the encoded key slices.

FIG. 23B is a flowchart illustrating an example of disperse storingsecure legacy data. The method begins with step 360 where a processingmodule (e.g., a memory control module) retrieves encoded key slices froma plurality of memories. For example, the plurality of memories isincluded in a legacy memory unit. The method continues at step 362 wherethe processing module decodes the encoded key slices utilizing an errorcoding dispersal storage function to produce an encryption key. Themethod continues at step 364 where the processing module retrievesencrypted data from a memory of the plurality of memories. The methodcontinues at step 366 where the processing module decrypts the encrypteddata utilizing the encryption key and in accordance with a decryptionfunction to produce data.

The method continues at step 368 where the processing module encodes thedata utilizing an error coding dispersal storage function to produce aplurality of sets of encoded data slices. The method continues at step370 where the processing module outputs the plurality of sets of encodeddata slices to at least some of the plurality of memories for storagetherein. The method continues at step 372 where the processing moduledeletes the encrypted data from the memory.

FIG. 24 is a flowchart illustrating another example of decommissioning amemory. The method begins with step 374 where a processing module (e.g.,of a memory control module) determines a priority access level of anencoded data slice stored on a memory device. The determining thepriority access level is based on at least one of a number of accessesof the encoded data slice, a service-level agreement, a data typeindicator, a predetermination, a lookup, a priority level of datacontained within the encoded data slice, a priority level of a useraccount associated with the encoded data slice, a message, and acommand. The method continues at step 376 where the processing moduledetermines an end-of-life memory level for the memory device. Thedetermining the end-of-life memory level is based on at least one of aservice life indicator, a historical performance record, an errormessage, an error rate, a performance test result, a predetermination, aquery, a message, and a command.

The method continues at step 378 where the processing module determineswhether to migrate the encoded data slice from the memory device basedon the priority access level and the end-of-life memory level. Thedetermining whether to migrate the encoded data slice includes at leastone of comparing a representation of the priority access level and theend-of-life memory level to a sliding migration scale and indicating themigration of the encoded data slice when the representation comparesunfavorably to the sliding migration scale. Such a representationincludes one or more of transforming, weighting, and combining. Forexample, processing module generates the representation as a differencebetween the priority access level and the end-of-life memory level whenthe priority access level indicates a high frequency of access of theencoded data slice and the end-of-life memory level indicates a level 2usability. In the example, the processing module indicates the migrationof encoded data slice when the representation is 1-2=−2 and comparesunfavorably to a sliding migration scale of zero. As another example,the processing module does not indicate the migration of encoded dataslice when the representation is 2−2=0 comparing favorably to thesliding migration scale of zero when the priority access level indicatesa low-frequency of access and the end-of-life memory level indicates alevel 2 usability. The method branches to step 380 when the processingmodule determines to migrate the encoded data slice. The method repeatsback to step 374 when the processing module determines to not migratethe encoded data slice.

The method continues at step 380 where the processing module identifiesanother memory device. For example, the processing module identifies theother memory device from a list of available memory devices. The methodcontinues at step 382 where the processing module facilitates migrationof the encoded data slice to another memory device. The migrating theencoded data slice includes determining to replicate the encoded dataslice and storing the encoded data slice in the other memory device. Thestoring the encoded data slice in the other memory device includesidentifying the other memory device, determining another end-of-lifememory level of the other memory device, comparing a representation ofthe priority access level and the other end-of-life memory level to asliding migration scale, and facilitating storing the encoded data slicein the other memory device when the representation compares favorably tothe sliding migration scale. For example, the processing moduleretrieves the encoded data slice from the memory device, identifies theanother memory device that is associated with a another end-of-lifememory level of 2 such that the representation of a priority accesslevel of 2 and the other end-of-life memory level of 2 comparesfavorably to a sliding migration scale of 0 (e.g., 2−2=0), and storesthe encoded data slice in the other memory device.

The method continues at step 34 where the processing module deletes theencoded data slice from the memory device. For example, the processingmodule writes zeros to the memory device. The method continues at step386 where the processing module updates a memory assignment table toindicate that the other memory device is storing the encoded data slice.Alternatively, or in addition to, a processing module updates the memoryassignment table to indicate that the memory device is no longer storingthe encoded data slice. The method continues at step 388 where theprocessing module tracks migration history of encoded data slices fromthe memory device. Alternatively, the processing module tracks themigration history from time to time independent of considering thepriority access level of the encoded data slice on the memory device.The tracking of the migration history includes at least one of receivingthe migration history, querying an event log, marking a history tablewhen an encoded data slice is migrated from the memory device, andsummarizing migration history.

The method continues at step 390 where the processing moduledecommissions the memory device based on the migration history.Decommissioning includes at least one of turning off power to the memorydevice, marking the memory device as unusable in a memory status table,sending an error message, activating a hot standby memory device,facilitating transferring remaining slices stored within the memorydevice, and updating the memory assignment table.

As may be used herein, the terms “substantially” and “approximately”provides an industry-accepted tolerance for its corresponding termand/or relativity between items. Such an industry-accepted toleranceranges from less than one percent to fifty percent and corresponds to,but is not limited to, component values, integrated circuit processvariations, temperature variations, rise and fall times, and/or thermalnoise. Such relativity between items ranges from a difference of a fewpercent to magnitude differences. As may also be used herein, theterm(s) “operably coupled to”, “coupled to”, and/or “coupling” includesdirect coupling between items and/or indirect coupling between items viaan intervening item (e.g., an item includes, but is not limited to, acomponent, an element, a circuit, and/or a module) where, for indirectcoupling, the intervening item does not modify the information of asignal but may adjust its current level, voltage level, and/or powerlevel. As may further be used herein, inferred coupling (i.e., where oneelement is coupled to another element by inference) includes direct andindirect coupling between two items in the same manner as “coupled to”.As may even further be used herein, the term “operable to” or “operablycoupled to” indicates that an item includes one or more of powerconnections, input(s), output(s), etc., to perform, when activated, oneor more its corresponding functions and may further include inferredcoupling to one or more other items. As may still further be usedherein, the term “associated with”, includes direct and/or indirectcoupling of separate items and/or one item being embedded within anotheritem. As may be used herein, the term “compares favorably”, indicatesthat a comparison between two or more items, signals, etc., provides adesired relationship. For example, when the desired relationship is thatsignal 1 has a greater magnitude than signal 2, a favorable comparisonmay be achieved when the magnitude of signal 1 is greater than that ofsignal 2 or when the magnitude of signal 2 is less than that of signal1.

As may also be used herein, the terms “processing module”, “module”,“processing circuit”, and/or “processing unit” may be a singleprocessing device or a plurality of processing devices. Such aprocessing device may be a microprocessor, micro-controller, digitalsignal processor, microcomputer, central processing unit, fieldprogrammable gate array, programmable logic device, state machine, logiccircuitry, analog circuitry, digital circuitry, and/or any device thatmanipulates signals (analog and/or digital) based on hard coding of thecircuitry and/or operational instructions. The processing module,module, processing circuit, and/or processing unit may have anassociated memory and/or an integrated memory element, which may be asingle memory device, a plurality of memory devices, and/or embeddedcircuitry of the processing module, module, processing circuit, and/orprocessing unit. Such a memory device may be a read-only memory, randomaccess memory, volatile memory, non-volatile memory, static memory,dynamic memory, flash memory, cache memory, and/or any device thatstores digital information. Note that if the processing module, module,processing circuit, and/or processing unit includes more than oneprocessing device, the processing devices may be centrally located(e.g., directly coupled together via a wired and/or wireless busstructure) or may be distributedly located (e.g., cloud computing viaindirect coupling via a local area network and/or a wide area network).Further note that if the processing module, module, processing circuit,and/or processing unit implements one or more of its functions via astate machine, analog circuitry, digital circuitry, and/or logiccircuitry, the memory and/or memory element storing the correspondingoperational instructions may be embedded within, or external to, thecircuitry comprising the state machine, analog circuitry, digitalcircuitry, and/or logic circuitry. Still further note that, the memoryelement may store, and the processing module, module, processingcircuit, and/or processing unit executes, hard coded and/or operationalinstructions corresponding to at least some of the steps and/orfunctions illustrated in one or more of the Figures. Such a memorydevice or memory element can be included in an article of manufacture.

The present invention has been described above with the aid of methodsteps illustrating the performance of specified functions andrelationships thereof. The boundaries and sequence of these functionalbuilding blocks and method steps have been arbitrarily defined hereinfor convenience of description. Alternate boundaries and sequences canbe defined so long as the specified functions and relationships areappropriately performed. Any such alternate boundaries or sequences arethus within the scope and spirit of the claimed invention. Further, theboundaries of these functional building blocks have been arbitrarilydefined for convenience of description. Alternate boundaries could bedefined as long as the certain significant functions are appropriatelyperformed. Similarly, flow diagram blocks may also have been arbitrarilydefined herein to illustrate certain significant functionality. To theextent used, the flow diagram block boundaries and sequence could havebeen defined otherwise and still perform the certain significantfunctionality. Such alternate definitions of both functional buildingblocks and flow diagram blocks and sequences are thus within the scopeand spirit of the claimed invention. One of average skill in the artwill also recognize that the functional building blocks, and otherillustrative blocks, modules and components herein, can be implementedas illustrated or by discrete components, application specificintegrated circuits, processors executing appropriate software and thelike or any combination thereof.

The present invention may have also been described, at least in part, interms of one or more embodiments. An embodiment of the present inventionis used herein to illustrate the present invention, an aspect thereof, afeature thereof, a concept thereof, and/or an example thereof. Aphysical embodiment of an apparatus, an article of manufacture, amachine, and/or of a process that embodies the present invention mayinclude one or more of the aspects, features, concepts, examples, etc.described with reference to one or more of the embodiments discussedherein. Further, from figure to figure, the embodiments may incorporatethe same or similarly named functions, steps, modules, etc. that may usethe same or different reference numbers and, as such, the functions,steps, modules, etc. may be the same or similar functions, steps,modules, etc. or different ones.

Unless specifically stated to the contra, signals to, from, and/orbetween elements in a figure of any of the figures presented herein maybe analog or digital, continuous time or discrete time, and single-endedor differential. For instance, if a signal path is shown as asingle-ended path, it also represents a differential signal path.Similarly, if a signal path is shown as a differential path, it alsorepresents a single-ended signal path. While one or more particulararchitectures are described herein, other architectures can likewise beimplemented that use one or more data buses not expressly shown, directconnectivity between elements, and/or indirect coupling between otherelements as recognized by one of average skill in the art.

The term “module” is used in the description of the various embodimentsof the present invention. A module includes a functional block that isimplemented via hardware to perform one or module functions such as theprocessing of one or more input signals to produce one or more outputsignals. The hardware that implements the module may itself operate inconjunction software, and/or firmware. As used herein, a module maycontain one or more sub-modules that themselves are modules.

While particular combinations of various functions and features of thepresent invention have been expressly described herein, othercombinations of these features and functions are likewise possible. Thepresent invention is not limited by the particular examples disclosedherein and expressly incorporates these other combinations.

What is claimed is:
 1. A method for managing memory in a storage networkcomprises: monitoring a service life indicator for a plurality ofsolid-state memory devices in the storage network; determining whether amemory device of the plurality of solid-state memory devices isapproaching an end-of-life event, wherein the end-of-life event is basedon a predetermined service life; in response to a determination that thememory device is approaching an end-of-life event, determining whetherto migrate one or more encoded data slices from the memory device to analternative memory device; in response to a decision to migrate the oneor more encoded data slices, selecting a migration scheme from aplurality of migration schemes for migrating the one or more encodeddata slices; and facilitating migrating the one or more encoded dataslices according to the selected migration scheme.
 2. The method ofclaim 1, further comprising: updating a memory assignment mechanism forthe one or more encoded data slices.
 3. The method of claim 2, whereinthe memory assignment mechanism is a memory assignment table.
 4. Themethod of claim 1, wherein the determining is based at least partiallyon a historical frequency of access for the memory device.
 5. The methodof claim 4, wherein the historical frequency of access pertains to writerequests.
 6. The method of claim 4, wherein the historical frequency ofaccess is determined based on at least one of: querying a memoryusability level table; testing a reprovisioned memory device;determining a memory assignment; receiving an error message; retrievingan error message history; receiving a message; obtaining historicalreliability data of similar reprovisioned memory devices; areprovisioned memory device age; a reprovisioned memory type; areprovisioned memory usage level; and and receiving a command.
 7. Themethod of claim 1, wherein the determining whether to migrate the one ormore encoded data slices from the memory device to an alternative memorydevice is based on at least one of: a status of the alternative memorydevice; a current memory utilization of the alternative memory device;an available memory indicator of the alternative memory device; apredetermination; a lookup; a message; and a command.
 8. The method ofclaim 1, wherein the alternative memory is not a solid-state memorydevice.
 9. The method of claim 1, further comprising: migrating the oneor more encoded data slices to the alternative memory device.
 10. Themethod of claim 1, wherein the facilitating migrating the one or moreencoded data slices includes instructing a storage network processormodule to store the one or more encoded data slices in the alternativememory device.
 11. The method of claim 10, wherein the migratingincludes decoding the one or more encoded data slices and re-encodingthe one or more encoded data slices according to dispersed storageparameters compatible with the alternative memory device.
 12. Acomputing device for a storage network comprises: one or more networkinterfaces; memory including operational instructions; and a processingmodule operably coupled to the memory and the one or more networkinterfaces, the processing module configured to execute the operationalinstructions to: monitor a service life indicator for a plurality ofsolid-state memory devices in the storage network; determine whether amemory device of the plurality of solid-state memory devices isapproaching an end-of-life event, wherein the end-of-life event is basedon a predetermined service life; in response to a determination that thememory device is approaching an end-of-life event, determine whether tomigrate one or more encoded data slices from the memory device to analternative memory device; in response to a decision to migrate the oneor more encoded data slices, select a migration scheme from a pluralityof migration schemes for migrating the one or more encoded data slices;and facilitate migrating the one or more encoded data slices accordingto the selected migration scheme.
 13. The computing device of claim 12,wherein the processing module is further configured to execute theoperational instructions to: update a memory assignment mechanism forthe one or more encoded data slices. a message and a command.
 14. Thecomputing device of claim 13, wherein the memory assignment mechanism isa memory assignment table.
 15. The computing device of claim 13, whereinthe determining is based at least partially on a historical frequency ofaccess for the memory device.
 16. The computing device of claim 15,wherein the historical frequency of access pertains to write requests.17. The computing device of claim 13, wherein the historical frequencyof access is determined based on at least one of: querying a memoryusability level table; testing a reprovisioned memory device;determining a memory assignment; receiving an error message; retrievingan error message history; receiving a message; obtaining historicalreliability data of similar reprovisioned memory devices; areprovisioned memory device age; a reprovisioned memory type; areprovisioned memory usage level; and and receiving a command.
 18. Thecomputing device of claim 13, wherein the processing module is furtherconfigured to execute the operational instructions to: determine whetherto migrate the one or more encoded data slices from the memory device toan alternative memory device is based on at least one of: a status ofthe alternative memory device; a current memory utilization of thealternative memory device; an available memory indicator of thealternative memory device; a predetermination; a lookup; a message; anda command.
 19. A method for managing memory in a storage networkcomprises: monitoring a service life for a plurality of solid-statememory devices in the storage network; determining whether one or morememory devices of the plurality of solid-state memory devices isapproaching an end-of-life event, wherein the end-of-life event is basedon a predetermined service life; in response to a determination that thememory device is approaching an end-of-life event, determining whetherto migrate one or more encoded data slices from the memory device to analternative memory device; in response to a decision to migrate the oneor more encoded data slices, facilitating migrating the one or moreencoded data slices according to a predetermined migration scheme. 20.The method of claim 19, wherein the predetermined migration scheme isselected from a plurality of migration schemes.